A read transaction in the memory subsystem of a processor-based computing system consists essentially of the following steps: (1) initiating, via the memory controller, the read operation; (2) generating the row address strobe/column address strobe (RAS/CAS) memory timing signals, and applying them to the memory bank targeted by the read operation; (3) once the read data is available on the memory bank's memory data bus, buffering the read data into a buffer coupled to the memory bank; and (4) transferring the data from the memory buffer into a data path buffer for storage until the data is placed onto the processor bus for transmission to the processor or device requesting the data. The time period between the initiation of a read operation by the memory controller within the memory subsystem and the time at which the read data is available on the memory data bus constitutes an access latency.
A write operation in a memory subsystem consists essentially of the following steps: (1) transferring the write data from the data path in the memory subsystem to a buffer coupled to the targeted memory bank; (2) initiating, via the memory controller, the write operation; and (3) generating the necessary RAS/CAS memory timing signals, and applying them to the memory bank targeted by the write operation.
In conventional memory subsystems, when a read or refresh operation is followed by a write operation, all of the read or refresh operation steps are performed prior to the initiation of the write operation steps. This results in a large transaction overhead, or "turnaround time." It is desired, therefore, to minimize the turnaround time associated with a read or refresh operation followed by a write operation in a memory subsystem of a processor-based computing system.